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| ?a _______________________________ . " 9 xz " 5 .t| 4 % ) 4 0 / & 5??-?3?? tsmo ???
?w . c q t ?????? ( c q t 3??????t!?b?3????2pb{ . " 9 x? ????s?qw?????t 7 &pb{???x3????? - 7 1 & $ -??? ??? !z
?zz - 7 1 & $ -3?????? z?t|??? z?? ? `?b{ o
? ( c q t3??????xz
:w ??, j???????0b? ? b uw 1 - -t?lo r^?z z???????w??? ?????m?b{ . " 9 x 7 o ?op ?^`z . ) [z . ) [z . ) [ x . ) [w, j?????? !z ?z?b{ 3a ?a?;tz??????? z?? ??lom?b{ . " 9 xz| 9 s c? ?? ? p?;pv? e? 5 2 ' 1?????? & 1 ?-?p ?^??b{ ??-?3?? _____________________ ( c q t 4 % ) 4 0 / & 5 ; 3a ( c q t???? ??? ????? ??????? " 5 .???? ? ? _______________________________ ?o 7 o ? ? ?? n 8 " / 4 *z * 5 6t| # f m m d p s ff? y . c q t ??? ? ??t? ( c q t 3????w!? ??? r ( c q t ???, j * t : . ) [z . ) [z . ) [z . ) [ 3a????a?;w' ?w? z? 3?????w 1 & $ -??? ?? ) ? 1 & $ -??? ??t|3?????? z? MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? ________________________________________________________________ maxim integrated products 1 19-1963; rev 0; 2/01 evaluation kit available j _______________________________ * ep = exposed pad a j??-?3??s?x7?tgl^?om?b{ part temp. range pin-package MAX3891ecb -40 c to +85 c 64 tqfp ep* 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 sdo- v cc gnd tqfp top view fil+ fil- v cc clkset rclk- rclk+ v cc pclko- pclko+ 52 53 49 50 51 v cc pdio v cc pdi1 gnd pdi15 v cc pdi14 v cc pdi13 v cc pdi12 v cc pdi11 v cc pdi10 v cc pdi9 v cc v cc pdi2 v cc pdi3 v cc pdi4 v cc pdi5 v cc pdi6 33 34 35 36 37 v cc pdi7 v cc pdi8 gnd v cc sclko+ sclko- v cc sos pclki- pclki+ v cc v cc sdo+ v cc slbo+ slbo- v cc 48 gnd gnd 64 v cc gnd 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 MAX3891 e? ? ___________________________________________________________________ ???t|7 y [???3??w ? tx?3tw????]b;<^m{ x x x n b y j n j d d p n ????3??tgl^?h o0xz?t???3tw?s???3????`h?wpb{?t?? \a? t|??t mmow y x ?mtv?b{ y?s o0w rtx?3tw?w???3???]? <^m{ MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? ?% to (v cc - 2v), cml loads = 50 ? ?% to v cc , t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc ..................................................................-0.5v to +5.0v all inputs, fil+, fil- .............................-0.5v to (v cc + 0.5v) output currents pecl outputs (sdo? sclko? pclko? ..................50ma cml outputs (slbo?...................................................15ma continuous power dissipation (t a = +85?) 64-pin tqfp-ep (derate 45.5mw/? above +85?) ........2.9w operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply current i cc pecl outputs unterminated, sos = iow 150 230 ma pecl outputs (sdo , sclko , pclko ) t a = 0? to +85? v cc v cc - 1.025 - 0.88 output voltage high v oh t a = -40? v cc v cc - 1.085 - 0.88 v t a = 0? to +85? v cc v cc - 1.81 - 1.62 output voltage low v ol t a = -40? v cc v cc - 1.83 - 1.555 v pecl inputs (pdi_, pclki , rclk ) input high voltage v ih v cc v cc - 1.16 - 0.88 v input low voltage v il v cc v cc - 1.81 - 1.48 v input current high pdi_, rclki i ih -10 +10 ? input current low pdi_, rclki programming input (clkset) clkset input current i clkset clkset = gnd or v cc 500 ? ttl input (sos) ttl input high voltage v ih 2.0 v ttl input low voltage v il 0.8 v ttl input high current i ih -10 +10 a ttl input low current i il -10 +10 a current mode logic (cml) outputs (slbo ) cml differential output voltage swing ? v od ? ? to v cc 100 400 mv cml single-ended output impedance r o 50 ? MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? _______________________________________________________________________________________ 3 note 1: ac characteristics are guaranteed by design and characterization. note 2: setup and hold times are relative to the rising edge of pclki+, measured by applying a 155.52mhz differential parallel clock with rise/fall time = 1ns (20% to 80%). see figure 1. note 3: setup and hold time measurements assume that the pclki and pdi signals are from the same source and have identical common-mode voltages, swings, and slew rates. ac electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? ?% to (v cc - 2v), cml loads = 50 ? ?% to v cc , t a = -40? to +85?. typical values are at t a = +25? and v cc = +3.3v, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units serial clock rate f sclk 2.488 ghz parallel data setup time t su (notes 2, 3) 300 ps parallel data-hold time t h (notes 2, 3) 700 ps pclko to pclki skew t skew figure 1 0 +4.0 ns output jitter generation (sclko ) jitter bandwidth = 12khz to 20mhz 3 ps rms pecl differential output (sdo , sclko ) rise/fall time t r , t f 20% to 80% 120 ps parallel input clock rate f pclki 155.52 mhz reference clock input (rclk ) rise/fall time t r , t f 20% to 80%, f = 155.52mhz 1.0 ns parallel clock output (pclko ) rise/fall time t r , t f 20% to 80% 1.0 ns serial-clock output (sclko ) to serial-data output (sdo ) delay t sclk-sd sclko rising edge to sdo edge 110 290 ps a j ?^ ? q _______________________________________________________________ (v cc = +3.3v , t a = +25?, unless otherwise noted.) 100 120 160 140 180 200 -50 0 -25 25 50 75 100 supply current vs. temperature MAX3891 toc01 temperature ( c) supply current (ma) pecl outputs unterminated serial-data output eye diagram MAX3891 toc02 100ps/div serial-data output jitter MAX3891 toc03 total wideband rms jitter = 2.059ps, peak-to-peak jitter = 16.70ps f rclk = 155.52mhz 5000ps/div z? ? ___________________________________________________________________ pin name function 1, 17, 33, 48, 49, 63 gnd ground 2, 5, 7, 10, 13, 14, 19, 21, 23, 25, 27, 29, 31, 32, 35, 37, 39, 41, 43, 45, 47, 51, 53, 56, 60, 64 v cc +3.3v supply voltage 3 slbo- system loopback negative output. enabled when sos is high. 4 slbo+ system loopback positive output. enabled when sos is high. 6 sos system loopback output select, ttl input. system loopback disabled when low. 8 sclko- negative pecl serial clock output 9 sclko+ positive pecl serial clock output 11 sdo- negative pecl serial data output 12 sdo+ positive pecl serial data output 15 pclki+ positive pecl parallel clock input. connect the incoming parallel-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal. 16 pclki- negative pecl parallel clock input. connect the incoming parallel-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal. 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 pdi15 to pdi0 single-ended pecl parallel data inputs. data is clocked on the pclki positive transition. pdi15 is transmitted first. 54 pclko+ positive pecl parallel clock output. use positive transition of pclko to clock the overhead management circuit. 55 pclko- negative pecl parallel clock output. use positive transition of pclko to clock the overhead management circuit. 57 rclk+ p osi ti ve refer ence c l ock inp ut. c onnect a pe c l-com pati bl e cr ystal reference cl ock to the rclk inp uts. 58 rclk- n egati ve refer ence c l ock inp ut. c onnect a pe c l-com pati bl e cr ystal reference cl ock to the rclk inp uts. 59 clkset reference clock rate programming pin: clkset = v cc : reference clock rate = 155.52mhz clkset = open: reference clock rate = 77.76mhz clkset = 20k ? to gnd: reference clock rate = 51.84mhz clkset = gnd: reference clock rate = 38.88mhz 61 fil- filter capacitor input. connect a 0.33 f capacitor between fil+ and fil- 62 fil+ filter capacitor input. connect a 0.33 f capacitor between fil+ and fil- ep exposed pad ground. this must be soldered to a circuit board for proper electrical and thermal performance (see exposed pad package information). MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? 4 _______________________________________________________________________________________ z? ? ; ???? 7 ?o ?y 3a???? ? z?{ 4 0 4u??wt?ts??b{ 3a???? y z?{ 4 0 4u??wt?ts??b{ 3a???? z? ? r{ 5 5 - ??{?wt3a????x?ts??b{ ? 1 & $ -3?????? z? y 1 & $ -3?????? z? ? 1 & $ -3?????? z? y 1 & $ -3?????? z? y 1 & $ -????? ??{ ! ?????? ??? 1 $ - , * ??t ? `?b{ ???x 1 $ - , * ??w y -?p? y^??\qt ??`o<^m{ ? 1 & $ -????? ??{ ! ?????? ??? 1 $ - , * ??t ? `?b{ ???x 1 $ - , * ??w y -?p? y^??\qt ??`o<^m{ 3????? 1 & $ -????? ??{???x 1 $ - , *w y -?p ?8 ??^??b{ 1 % * u7 st ?^??b{ y 1 & $ -????? z?{ 1 $ - , 0w y -??|???? rgs?w???t?;`?b{ ? 1 & $ -????? z?{ 1 $ - , 0w y -??|???? rgs?w? ??t?;`?b{ y??????? ??{ 1 & $ -??????, j???? 3 $ - , ?? t ? `o<^m{ ???????? ??{ 1 & $ -??????, j???? 3 $ - , ?? t ? `o<^m{ , j?????????? z? $ - , 4 & 5 7 $ $ , j????? . ) [ $ - , 4 & 5 |??, j????? . ) [ $ - , 4 & 5 l ? u p ( / %, j????? . ) [ $ - , 4 & 5 ( / %, j????? . ) [ ??????? ??{ ' * - q ' * - wt '???? ? `o<^m{ ??????? ??{ ' * - q ' * - wt '???? ? `o<^m{ ????{ & ys ?> $t| ? $ q ? ??txz\??s?, xt??? ?zb? ?auk??b ???????-?w ??? { MAX3891 _______________________________________________________________________________________ 5 ?i _______________________________ . " 9 x ??? ?w . c q t???? ( c q t 3??????t!?`?b $ { . " 9 x ??? ?? ???z ???3???z m?t|???????z 1 & $ - z????t| * t : r 1 - - ? * t :??a??z?????? ??z ?y m? c ?+ 7 $ 0 z?-??p? r t? rlom?b{ 1 - -x z?3???w???t?;b? o ? ( c q t , j???? r` ?b{\w???xz ? ? . ) [z . ) [z . ) [x . ) [, j??? ?? 3 $ - , t?lo \ r^? ?b{ ! ??????xz????? ?? ?? 1 $ - , * wq u? -?p . " 9 t ?8 ??^? ?b{ y s ?^xz?? ???u?? ??? z? ?? 1 $ - , 0 ?, jtf ^?h ? u 4 , & 8 op???^?om? ?t- a^??b{ 1 $ - , 0xz r^?h ( c q t w o ?3??? ??? ??? *`h?wpb{ 1 $ - , *t 0b? 1 $ - , 0w??w?0 c?x ? o tpb{\?xz 1 $ - , 0q u???w ?? [`om?b{ 1 $ - , *wq u??xz\wti\?d quk? ?b $ { 3a???? . " 9 xz3a????a???q? ?ot ?-^?om?b{ . " 9 w???? z? 4 - # 0 xz?3????2 . " 9 w?? ?? ??t ? ? `o3a ???o\qu pv?b{ 4 - # 0 z???tb?txz 5 5 -?? ?? ??? 4 0 4 ??t1c`?b{ 4 0 4??? ?? ? m?b? ??q ?a?w? . " 9 w 4 * 4??? ??w m?t??;pv?b{ $ ????? $ t skew pclko pclki parallel input data (pdi_) note: signals shown are differential. for example, pcklo = (pclk0+) - (pclko-). *pdi i5 = d15; pdi14 = d14, . . . pdi0 = d0. this figure is not intended to show a specific timing relationship between parallel input data and serial output data. t su t h d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15* 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? MAX3891 6 _______________________________________________________________________________________ ??-?3?? ?c _________________ ????t|???w e ????t|???w?7xz?? ?? ?? 1 $ - , * q???? ? ?? ?? 1 % * @ u ?a 1?t?rom?q> `om?b{\?? xw ??x ?w ? ?yz ?? ?t|????p sz?ys??d?{ 1 $ - , *q 1 % * @u g ?t?s? ? xzfwm?-?t ???h?t????t| ???w e? . yb? ?auk??b{ u % & ( xz 1 $ - , *q 1 % * @wt gvsmuk? ?w e t? q`o [^??b{ \\pz u 5 x?????t|??? ?? ??w -? ? z 7 0 ) t| 7 0 - xf?g??? ???t|??? ?? ??w ??? ?yt| ? ?yz 7 $ . % * ' ' x?????t|??? ?? ??w ? ?yw)pb{ t vcm t vv deg diff t oh ol = ? ? ? ? ? ? 06 . - MAX3891 16-bit parallel input register 16-bit parallel shift register phase/freq detect pecl pdi15 pdi1 pdi0 pclki+ pclki- rclk+ rclk- pecl pecl buf pecl pecl pecl pecl cml slbo+ sos sdo+ sdo- slbo- sclko+ sclko- pecl shift latch filter fil+ fil- clkset pclko+ pclko- prescaler vco divide by 16 $ ????3??????? 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? _______________________________________________________________________________________ 7 e t^?h???? u 4 6 " % + t|??? u ) " % + w exp ^??b{ t suadj ( x t hadj ) = t su ( x t h ) + t deg 1 & $ - ? z?w 4 z rg . " 9 w 1 & $ -???t|??? * 0x & ~t? ?b? ?auk??b{ $ t| tz 1 & $ - z? 4 z rgw mo??`?b{ & ~s 4 z rg??otxz 7 $ $ 7 t 0`o ? ? ?b?s?t|??e? ??u e t^?h ; ???u ?apb{ 7 $ $ 7 ?oub;pvsm ?xza?? sas???lo <^m{ " $????u ?as ?xz???? ???u ? xa?? sa % $ 4 zw?t r??ot`o<^m{7?w q ?- ab?h?txz ) ? z? 4 % 0 t| 1 $ - , 0 w ?yu?`om? ?auk??b{ ?vt???? z? . " 9 w3a???? z? 4 - # 0 x $ . - ??pb{ . " 9 ?vt?? ?? $ . - z? s?txz 7 $ $?w ? w o ?o 4 zu??om?b $ {\??w z?xz 4 z rg^?h ? w ; ????? ?b??otslom?b{ ???uo 7?w q ? ??txz?h? * t???uo? ?;`o<^m{ ?otx????????a`z ???? w ? x yx`ozd sx tp??? x?;`o <^m{?hz . " 9 w???t|??? ? z? qw?????txz??e???u e t^?h ; ?????;`o<^m{ ???????-? ________ e??????? & 1 5 2 ' 1xl ?;t ? ?u??o ?m&?? ?`om?b{ . " 9 & 1x ? ; ?pw?m??????t ???? ?z b? ?auk??b{ ?? ?c __________________________ transistor count: 1712 process: bipolar MAX3891 8 _______________________________________________________________________________________ $ 1 & $ - ?? 4 z rgw ? rd smo overhead generation c. ac-coupling to non-pecl outputs z 0 = 50 ? 82 ? 82 ? 130 ? 130 ? 0.1 f +3.3v 0.1 f z 0 = 50 ? MAX3891 pecl inputs overhead generation b. dc-coupling to non-pecl outputs z 0 = 50 ? 130 ? 130 ? 82 ? 82 ? v = +3.3v (v cc - 2v) z 0 = 50 ? MAX3891 pecl inputs overhead generation a. pecl terminations z 0 = 50 ? 50 ? 50 ? z 0 = 50 ? MAX3891 pecl inputs pecl terminations dc-coupling to pecl outputs ac-coupling to non-pecl outputs 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? MAX3891 _______________________________________________________________________________________ 9 $ 1 & $ - z? 4 z rgw ? rd smo b. thevenin-equivalent dc termination z 0 = 50 ? 82 ? 82 ? 130 ? 130 ? +3.3v z 0 = 50 ? pecl inputs 0.1 f 0.1 f a. pecl output termination z 0 = 50 ? 50 ? 50 ? z 0 = 50 ? high impedance inputs MAX3891 MAX3891 sclko+ or sdo+ sclko- or sdo- sclko+ or sdo+ sclko- or sdo- gnd output circuit input circuit v cc v cc 50 ? 50 ? 50 ? slb0+ slb1+ slb1- slb0- esd sructure 50 ? MAX3891 max3881 $ ?vt???? 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? 10 ______________________________________________________________________________________ v cc ttl sos clkset rclk- rclk+ MAX3891 max3869 +3.3v +3.3v term term term term term term term term term term term term term term term 0.33 f fil+ fil- slbo+ optional connection to max3881 for system loopback testing this symbol represents a transmission line of characteristic impedance z 0 = 50 ? this symbol represents a pecl termination with a thevenin equivalent of 50 ? to (v cc - 2v) note: refer to applications information section for more on pecl input and output terminations slbo- pclki pclki pclki- pclki+ pdi15 pdi0 sclko- sclko+ sdo- sdo+ overhead generation 155mhz reference clock input a j??-?3??s? _____________________________________________________ MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? ______________________________________________________________________________________ 11 64l, tqfp.eps ?-? _________________________________________________________________ MAX3891 7z ( c q tz 4 % ) 4 0 / & 5 3????2 ??? rt| - 7 1 & $ - ?? ? ?3tpx ? .u?3t a ?p?q^?om?s???ws?w?;tmmox y ??j?d?{s? ?????xt^? om?d?{ ?3tx 5's`ts?t|?7?!?b?vb?-y`?b{ 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products is a registered trademark of maxim integrated products. ?-? v ____________________________________________________________ b eg 3 ? f? n y s b ? > ? o ? ?? 5 & - ' " 9 |
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